With the increased size of software and highly complicated hardware structures, time required for executing an information processing apparatus such as a computer, copier, multifunctional product (MFP), or embedded system tends to increase.
To reduce the execution time of the information processing apparatus, various approaches have been made. Japanese Patent Application Publication No. 2009-175904 describes a technique of reducing the execution time by causing a plurality of processors to concurrently transfer programs needed for execution from a memory, thus reducing the overall time for execution. This technique, however, prevents other software programs from using the processors until the programs are transferred. Further, providing the plurality of processors increases the overall manufacturing costs.
Japanese Patent Application Publication No. 2006-134025 describes a technique of increasing the processing speeds by setting initial set values of hardware resources and software resources in parallel, using a plurality of direct memory access controllers (DMACs). More specifically, the DMACs perform data setting in the order specified by a data setting command list that lists data setting commands to be executed by the plurality of DMACs. This technique has a drawback such that data setting may not be appropriately performed if the initialization conditions change.
Japanese Patent Application Publication No. 2008-299793 describes a technique of reducing the execution time by initializing a hardware controller before execution of a processor, specifically, by initializing a RAM controller before initialization of a CPU. Since initialization of the RAM only requires short time, such as 1 millieconds, only initializing the RAM beforehand does not contribute much to the decrease in execution time.